From: Tom Rini On IBM 40x and IBM 4xx (or more specifically, all Book E processors), the Save/Restor Registers 2 and 3 Critical Save and Restore Registers 0 and 1 are logically and functionally equivalent. And since the 40x is the early variant on the Book E model, make generic 4xx/BookE code refer to CSRR0/CSRR1, and map these to SRR2/SRR3 on 40x. --- 25-akpm/arch/ppc/kernel/entry.S | 4 ++-- 25-akpm/include/asm-ppc/reg_booke.h | 7 +++++++ 2 files changed, 9 insertions(+), 2 deletions(-) diff -puN arch/ppc/kernel/entry.S~ppc32-save-restore-fix arch/ppc/kernel/entry.S --- 25/arch/ppc/kernel/entry.S~ppc32-save-restore-fix Tue Feb 10 12:54:27 2004 +++ 25-akpm/arch/ppc/kernel/entry.S Tue Feb 10 12:54:27 2004 @@ -689,8 +689,8 @@ ret_from_crit_exc: mtspr SPRN_ESR,r10 lwz r11,_NIP(r1) lwz r12,_MSR(r1) - mtspr SRR2,r11 - mtspr SRR3,r12 + mtspr CSRR0,r11 + mtspr CSRR1,r12 lwz r9,GPR9(r1) lwz r12,GPR12(r1) lwz r10,crit_sprg0@l(0) diff -puN include/asm-ppc/reg_booke.h~ppc32-save-restore-fix include/asm-ppc/reg_booke.h --- 25/include/asm-ppc/reg_booke.h~ppc32-save-restore-fix Tue Feb 10 12:54:27 2004 +++ 25-akpm/include/asm-ppc/reg_booke.h Tue Feb 10 12:54:27 2004 @@ -130,6 +130,8 @@ do { \ #define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ #define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ #define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ +#define SPRN_CSRR0 SPRN_SRR2 /* Critical Save and Restore Register 0 */ +#define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */ #endif /* Bit definitions for the DBSR. */ @@ -237,8 +239,13 @@ do { \ #define SGR_GUARDED 1 /* Speculative fetching disallowed. */ /* Short-hand for various SPRs. */ +#ifdef CONFIG_BOOKE #define CSRR0 SPRN_CSRR0 /* Critical Save and Restore Register 0 */ #define CSRR1 SPRN_CSRR1 /* Critical Save and Restore Register 1 */ +#else +#define CSRR0 SPRN_SRR2 /* Logically and functionally equivalent. */ +#define CSRR1 SPRN_SRR3 /* Logically and functionally equivalent. */ +#endif #define DCMP SPRN_DCMP /* Data TLB Compare Register */ #define SPRG4R SPRN_SPRG4R /* Supervisor Private Registers */ #define SPRG5R SPRN_SPRG5R _