commit 5863638598f5e4f64d2f85b03f376383ca1f2ab7 Author: Alice Chao Date: Mon Aug 11 21:11:26 2025 +0800 scsi: ufs: host: mediatek: Fix invalid access in vccqx handling Add a NULL check before accessing the 'vccqx' pointer to prevent invalid memory access. This ensures that the function safely handles cases where 'vccq' and 'vccq2' are not initialized, improving the robustness of the power management code. Signed-off-by: Alice Chao Reviewed-by: Peter Wang Signed-off-by: Peter Wang Link: https://lore.kernel.org/r/20250811131423.3444014-11-peter.wang@mediatek.com Signed-off-by: Martin K. Petersen commit 878ed88c50bfb14d972dd3b86a1c8188c58de4e5 Author: Peter Wang Date: Mon Aug 11 21:11:25 2025 +0800 scsi: ufs: host: mediatek: Change reset sequence for improved stability Modify the reset sequence to ensure that the device reset pin is set low before the host is disabled. This change enhances the stability of the reset process by ensuring the correct order of operations. Signed-off-by: Peter Wang Link: https://lore.kernel.org/r/20250811131423.3444014-10-peter.wang@mediatek.com Signed-off-by: Martin K. Petersen commit bacb96ce06c05804fae4bfd38c4058b6d4c423b3 Author: Peter Wang Date: Mon Aug 11 21:11:24 2025 +0800 scsi: ufs: host: mediatek: Fix UniPro setting for MT6989 Set the UniPro attribute 0xD09E[4] bit to enable the 1144 functions specifically for the MT6989 platform. This adjustment ensures proper functionality and compatibility with the MT6989 hardware. Signed-off-by: Peter Wang Link: https://lore.kernel.org/r/20250811131423.3444014-9-peter.wang@mediatek.com Signed-off-by: Martin K. Petersen commit f1617ecf18aaf222482f683f44ab4b155976539d Author: Peter Wang Date: Mon Aug 11 21:11:23 2025 +0800 scsi: ufs: host: mediatek: Optimize power mode change handling Optimize the power mode change process by skipping the adaptation setting toggle if the requested power mode configuration is already applied. This enhancement reduces unnecessary operations, improving efficiency during power mode transitions. Signed-off-by: Peter Wang Link: https://lore.kernel.org/r/20250811131423.3444014-8-peter.wang@mediatek.com Signed-off-by: Martin K. Petersen commit 979feee0cf43b32d288931649d7c6d9a5524ea55 Author: Alice Chao Date: Mon Aug 11 21:11:22 2025 +0800 scsi: ufs: host: mediatek: Assign power mode userdata before FASTAUTO mode change Assign power mode userdata settings before transitioning to FASTAUTO power mode. This ensures that default timeout values are set for various parameters, enhancing the reliability and performance of the power mode change process. Signed-off-by: Alice Chao Reviewed-by: Peter Wang Signed-off-by: Peter Wang Link: https://lore.kernel.org/r/20250811131423.3444014-7-peter.wang@mediatek.com Signed-off-by: Martin K. Petersen commit 7212d624f8638f8ea8ad1ecbb80622c7987bc7a1 Author: Peter Wang Date: Mon Aug 11 21:11:21 2025 +0800 scsi: ufs: host: mediatek: Fix PWM mode switch issue Address a failure in switching to PWM mode by ensuring proper configuration of power modes and adaptation settings. The changes include checks for SLOW_MODE and adjustments to the desired working mode and adaptation configuration based on the device's power mode and hardware version. Signed-off-by: Peter Wang Link: https://lore.kernel.org/r/20250811131423.3444014-6-peter.wang@mediatek.com Signed-off-by: Martin K. Petersen commit 86a678a25108705657e2f3bb00c42f9e5e5d692b Author: Peter Wang Date: Mon Aug 11 21:11:20 2025 +0800 scsi: ufs: host: mediatek: Fine-tune clock scaling Disable clock scaling for UFS versions below 4.0. Clock scaling is unnecessary for these versions, and this change ensures that the feature is only enabled for compatible UFS versions. Signed-off-by: Peter Wang Link: https://lore.kernel.org/r/20250811131423.3444014-5-peter.wang@mediatek.com Signed-off-by: Martin K. Petersen commit f91c6c70d103a619c58aa02bddf3c27c6433556a Author: Peter Wang Date: Mon Aug 11 21:11:19 2025 +0800 scsi: ufs: host: mediatek: Add debug information for Auto-Hibern8 Enhance the clock gating logic by adding debug information for the Auto-Hibern8 (AHIT) register. This additional logging aids in troubleshooting by providing insights into the AHIT configuration when the clock is not turned off as expected. Signed-off-by: Peter Wang Link: https://lore.kernel.org/r/20250811131423.3444014-4-peter.wang@mediatek.com Signed-off-by: Martin K. Petersen commit aa86602a483ba48f51044fbaefa1ebbf6da194a4 Author: Peter Wang Date: Mon Aug 11 21:11:18 2025 +0800 scsi: ufs: host: mediatek: Fix auto-hibern8 timer configuration Move the configuration of the Auto-Hibern8 (AHIT) timer from the post-link stage to the 'fixup_dev_quirks' function. This change allows setting the AHIT based on the vendor requirements: (a) Samsung: 3.5 ms (b) Micron: 2 ms (c) Others: 1 ms Additionally, the clock gating timer is adjusted based on the AHIT scale, with a maximum setting of 10 ms. This ensures that the clock gating delay is appropriately configured to match the AHIT settings. Signed-off-by: Peter Wang Link: https://lore.kernel.org/r/20250811131423.3444014-3-peter.wang@mediatek.com Signed-off-by: Martin K. Petersen commit 6c00c493a344b65fb0a356cb3f328a647085687b Author: Peter Wang Date: Mon Aug 11 21:11:17 2025 +0800 scsi: ufs: host: mediatek: Simplify variable usage Simplify the code by using 'info->vcc' instead of 'hba->vreg_info.vcc', as they refer to the same value. This change improves code readability. Signed-off-by: Peter Wang Link: https://lore.kernel.org/r/20250811131423.3444014-2-peter.wang@mediatek.com Signed-off-by: Martin K. Petersen commit 149009f2dc6f781f490a13264eaa565281e4d490 Author: Krzysztof Kozlowski Date: Thu Jul 31 09:15:54 2025 +0200 scsi: ufs: qcom: dt-bindings: Split SM8650 and similar The binding for Qualcomm SoC UFS controllers grew and it will grow further. Split SM8650 and SM8750 UFS controllers which: 1. Do not reference ICE as IO address space, but as phandle, 2. Have same order of clocks. 3. Have MCQ I/O address space. Document that MCQ address space as optional to maintain backwards compatibility and because Linux drivers can operate perfectly fine without it (thus without MCQ feature). Linux driver already uses "mcq" as possible name for "reg-names" property. The split allows easier review and maintenance of the binding. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250731-dt-bindings-ufs-qcom-v2-3-53bb634bf95a@linaro.org Reviewed-by: Rob Herring (Arm) Acked-by: Manivannan Sadhasivam Signed-off-by: Martin K. Petersen commit 655c8f511926250e0da9e8b1a9b8f1cf2c173b41 Author: Krzysztof Kozlowski Date: Thu Jul 31 09:15:53 2025 +0200 scsi: ufs: qcom: dt-bindings: Split SC7180 and similar The binding for Qualcomm SoC UFS controllers grew and it will grow further. Split SC7180 and several other devices which: 1. Do not reference ICE as I/O address space, but as a phandle, 2. Have same order of clocks (SC7180 has one clock less than SC7280 and other variants in split binding). The split allows easier review and maintenance of the binding. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250731-dt-bindings-ufs-qcom-v2-2-53bb634bf95a@linaro.org Reviewed-by: Rob Herring (Arm) Signed-off-by: Martin K. Petersen commit 7f224967aee7d5ad88b6db76ca161be622ae7b34 Author: Krzysztof Kozlowski Date: Thu Jul 31 09:15:52 2025 +0200 scsi: ufs: qcom: dt-bindings: Split common part to qcom,ufs-common.yaml The binding for Qualcomm SoC UFS controllers grew and it will grow further. It already includes several conditionals, partially for difference in handling encryption block (ICE, either as phandle or as I/O address space) but it will further grow for MCQ. Prepare for splitting this one big binding into several ones for common group of devices by defining common part for all Qualcomm UFS schemas. This only moves code, no functional impact expected. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250731-dt-bindings-ufs-qcom-v2-1-53bb634bf95a@linaro.org Reviewed-by: Rob Herring (Arm) Signed-off-by: Martin K. Petersen